134 lines
4.1 KiB
Rust
134 lines
4.1 KiB
Rust
use ch32_hal as hal;
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use hal::println;
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pub unsafe fn init_gpio_irq(pin: u8, port: u8, rising: bool, falling: bool) {
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critical_section::with(|_| {
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#[cfg(feature = "enable_print")]
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println!("init_gpio_irq {pin}:{port}");
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let exti = &hal::pac::EXTI;
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let afio = &hal::pac::AFIO;
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let port = port as u8;
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let pin = pin as usize;
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// let b = afio.exticr().read();
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afio.exticr().modify(|w| w.set_exti(pin, port));
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exti.intenr().modify(|w| w.set_mr(pin, true)); // enable interrupt
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exti.rtenr().modify(|w| w.set_tr(pin, rising));
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exti.ftenr().modify(|w| w.set_tr(pin, falling));
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});
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}
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pub fn clear_interrupt(coin_pin: u8, button_pin: u8) -> [bool; 2] {
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let mut output = [false, false];
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let exti = &hal::pac::EXTI;
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let coin_pin = coin_pin as usize;
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let button_pin = button_pin as usize;
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exti.intenr().modify(|w| w.set_mr(coin_pin, false)); // disable interrupt
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exti.intenr().modify(|w| w.set_mr(button_pin, false)); // disable interrupt
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let bits = exti.intfr().read();
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// We don't handle or change any EXTI lines above 24.
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let bits = bits.0 & 0x00FFFFFF;
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#[cfg(feature = "enable_print")]
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println!("bits: {bits:08x}");
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// coin_flag
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if (bits & (0x1 << coin_pin)) != 0x0 {
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#[cfg(feature = "enable_print")]
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println!("coin irq!");
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output[0] = true;
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}
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// button_flag
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if (bits & (0x1 << button_pin)) != 0x0 {
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#[cfg(feature = "enable_print")]
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println!("main_btn irq!");
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output[1] = true;
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}
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// Clear pending - Clears the EXTI's line pending bits.
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exti.intfr().write(|w| w.0 = bits);
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use hal::pac::Interrupt;
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unsafe {
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qingke::pfic::unpend_interrupt(Interrupt::EXTI7_0 as u8);
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};
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// exti.intenr().modify(|w| w.0 = w.0 & !bits);
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exti.intenr().modify(|w| w.set_mr(coin_pin, true)); // enable interrupt
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exti.intenr().modify(|w| w.set_mr(button_pin, true)); // enable interrupt
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output
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}
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/// enter standby (SLEEPDEEP) mode, with WFE enabled.
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/// from CH32V003 reference manual 2.3.1:
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/// entry:
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/// 1. configure core register control bit: SLEEPDEEP=1 | PDDS = 1
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/// 2. configure external interrupt register to mask all but EXTI7_0
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/// 3. execute WFI or WFE (optionally SEVONPEND) and SLEEPONEXIT
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/// * (probably WFI?)
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/// exit:
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/// 1. any interrupt/event (set in external interrupt register)
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pub unsafe fn enter_standby() {
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critical_section::with(|_| {
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use hal::pac::Interrupt;
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use qingke_rt::CoreInterrupt;
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// configure core register control bit (SLEEPDEEP=1 | PDDS=1)
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let pfic = &hal::pac::PFIC;
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pfic.sctlr().modify(|w| {
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// we only want to wake on enabled interrupts
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w.set_sevonpend(false);
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// we want to enable deep sleep
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w.set_sleepdeep(true);
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w.set_wfitowfe(false);
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w.set_sleeponexit(false);
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});
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// set PDDS=1:
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// get current value of PWR_CTLR
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let mut reg: u32 = 0x4000_7000;
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let mut val: u32 = unsafe { (reg as *mut u32).read_volatile() };
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// modify PDDS
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val |= 1 << 1; // PWR_CTLR[1] -> PDDS
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unsafe {
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(reg as *mut u32).write_volatile(val);
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}
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// // disable all exti interrupts
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let exti = &hal::pac::EXTI;
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// exti.intenr().write(| w| {
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// w.0 = 0x00000000;
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// // w.set_mr(pin, true);
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// // w.set_mr(pin, true);
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// });
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// clear all pending exti interrupts
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let bits = 0xFFFFFFFF;
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exti.intfr().write(|w| w.0 = bits);
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// enable all exti interrupts
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let exti = &hal::pac::EXTI;
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exti.intenr().write(|w| {
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w.0 = 0x00FFFFFF;
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// w.set_mr(pin, true);
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// w.set_mr(pin, true);
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});
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unsafe {
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qingke::pfic::disable_interrupt(CoreInterrupt::SysTick as u8);
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qingke::pfic::enable_interrupt(Interrupt::EXTI7_0 as u8);
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}
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// execute WFI
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#[cfg(feature = "enable_print")]
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println!("WFI CONFIGURED HOPEFULLY");
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});
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}
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